cd targets/epm570 && /opt/altera9.1sp1/quartus/bin/quartus_map  top
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2010 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Sun May 23 18:00:05 2010
Info: Command: quartus_map top
Info: Found 1 design units, including 1 entities, in source file top.v
    Info: Found entity 1: top
Info: Found 1 design units, including 1 entities, in source file /home/gsinai/Build/Altera/Projects/Counter/cpld/verilog/counter.v
    Info: Found entity 1: counter
Info: Found 1 design units, including 1 entities, in source file /home/gsinai/Build/Altera/Projects/Counter/cpld/verilog/i2c.v
    Info: Found entity 1: i2c
Info: Elaborating entity "top" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at top.v(39): truncated value with size 32 to match size of target (3)
Warning (10027): Verilog HDL or VHDL warning at the top.v(94): index expression is not wide enough to address all of the elements in the array
Warning (10034): Output port "LED[4..3]" at top.v(16) has no driver
Info: Elaborating entity "counter" for hierarchy "counter:u1"
Info: Elaborating entity "i2c" for hierarchy "i2c:u2"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "LED[3]" is stuck at GND
    Warning (13410): Pin "LED[4]" is stuck at GND
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
    Info: Register "counter:u1|counter_ru[30]" lost all its fanouts during netlist optimizations.
    Info: Register "counter:u1|counter_ru[31]" lost all its fanouts during netlist optimizations.
Info: Implemented 226 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 10 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 212 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Peak virtual memory: 178 megabytes
    Info: Processing ended: Sun May 23 18:00:08 2010
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:03
cd targets/epm570 && /opt/altera9.1sp1/quartus/bin/quartus_fit  top
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2010 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Sun May 23 18:00:10 2010
Info: Command: quartus_fit top
Info: Selected device EPM570T100C3 for design "top"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100C3 is compatible
Info: Timing-driven compilation is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal "CLOCK_R" to use Global clock in PIN 12
    Info: Destination "OSC[0]" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "CLOCK_X" to use Global clock in PIN 14
    Info: Destination "LED[5]" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "SCL" to use Global clock in PIN 64
    Info: Destination "i2c:u2|start_neg" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Extra Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00
Info: Finished register packing
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to register delay of 3.971 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y6; Fanout = 21; REG Node = 'i2c:u2|data_o_reg[1]'
    Info: 2: + IC(0.326 ns) + CELL(0.571 ns) = 0.897 ns; Loc. = LAB_X6_Y6; Fanout = 1; COMB Node = 'i2c:u2|data_i_reg~0'
    Info: 3: + IC(1.109 ns) + CELL(0.319 ns) = 2.325 ns; Loc. = LAB_X5_Y5; Fanout = 1; COMB Node = 'i2c:u2|data_i_reg~1'
    Info: 4: + IC(0.168 ns) + CELL(0.571 ns) = 3.064 ns; Loc. = LAB_X5_Y5; Fanout = 1; COMB Node = 'i2c:u2|data_i_reg~3'
    Info: 5: + IC(0.168 ns) + CELL(0.739 ns) = 3.971 ns; Loc. = LAB_X5_Y5; Fanout = 1; REG Node = 'i2c:u2|data_i_reg[7]'
    Info: Total cell delay = 2.200 ns ( 55.40 % )
    Info: Total interconnect delay = 1.771 ns ( 44.60 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 9% of the available device resources
    Info: Peak interconnect usage is 9% of the available device resources in the region that extends from location X0_Y0 to location X13_Y8
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 185 megabytes
    Info: Processing ended: Sun May 23 18:00:14 2010
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:04
cd targets/epm570 && /opt/altera9.1sp1/quartus/bin/quartus_asm  top
Info: *******************************************************************
Info: Running Quartus II Assembler
    Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2010 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Sun May 23 18:00:16 2010
Info: Command: quartus_asm top
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 157 megabytes
    Info: Processing ended: Sun May 23 18:00:17 2010
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01
cd targets/epm570 && /opt/altera9.1sp1/quartus/bin/quartus_tan  top
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2010 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Sun May 23 18:00:18 2010
Info: Command: quartus_tan top
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLOCK_R" is an undefined clock
    Info: Assuming node "SCL" is an undefined clock
    Info: Assuming node "SDA" is an undefined clock
    Info: Assuming node "CLOCK_X" is an undefined clock
Info: Slack time is -974 ps for clock "CLOCK_R" between source register "counter:u1|count_r" and destination register "counter:u1|counter_ru[10]"
    Info: Fmax is 201.05 MHz (period= 4.974 ns)
    Info: + Largest register to register requirement is 3.557 ns
        Info: + Setup relationship between source and destination is 4.000 ns
            Info: + Latch edge is 4.000 ns
                Info: Clock period of Destination clock "CLOCK_R" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "CLOCK_R" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLOCK_R" to destination register is 2.610 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_12; Fanout = 72; CLK Node = 'CLOCK_R'
                Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.610 ns; Loc. = LC_X2_Y5_N0; Fanout = 3; REG Node = 'counter:u1|counter_ru[10]'
                Info: Total cell delay = 1.609 ns ( 61.65 % )
                Info: Total interconnect delay = 1.001 ns ( 38.35 % )
            Info: - Longest clock path from clock "CLOCK_R" to source register is 2.610 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_12; Fanout = 72; CLK Node = 'CLOCK_R'
                Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.610 ns; Loc. = LC_X3_Y6_N9; Fanout = 5; REG Node = 'counter:u1|count_r'
                Info: Total cell delay = 1.609 ns ( 61.65 % )
                Info: Total interconnect delay = 1.001 ns ( 38.35 % )
        Info: - Micro clock to output delay of source is 0.235 ns
        Info: - Micro setup delay of destination is 0.208 ns
    Info: - Longest register to register delay is 4.531 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y6_N9; Fanout = 5; REG Node = 'counter:u1|count_r'
        Info: 2: + IC(0.842 ns) + CELL(0.319 ns) = 1.161 ns; Loc. = LC_X2_Y6_N4; Fanout = 2; COMB Node = 'counter:u1|ready_r0~0'
        Info: 3: + IC(0.497 ns) + CELL(0.319 ns) = 1.977 ns; Loc. = LC_X2_Y6_N9; Fanout = 30; COMB Node = 'counter:u1|counter_ru[3]~2'
        Info: 4: + IC(1.454 ns) + CELL(1.100 ns) = 4.531 ns; Loc. = LC_X2_Y5_N0; Fanout = 3; REG Node = 'counter:u1|counter_ru[10]'
        Info: Total cell delay = 1.738 ns ( 38.36 % )
        Info: Total interconnect delay = 2.793 ns ( 61.64 % )
Warning: Can't achieve timing requirement Clock Setup: 'CLOCK_R' along 322 path(s). See Report window for details.
Info: Slack time is -2.339 ns for clock "SCL" between source register "i2c:u2|index[8]" and destination register "i2c:u2|data_i_reg[7]"
    Info: Fmax is 115.23 MHz (period= 8.678 ns)
    Info: + Largest register to register requirement is 1.557 ns
        Info: + Setup relationship between source and destination is 2.000 ns
            Info: + Latch edge is 2.000 ns
                Info: Clock period of Destination clock "SCL" is 4.000 ns with inverted offset of 2.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "SCL" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "SCL" to destination register is 2.526 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_64; Fanout = 36; CLK Node = 'SCL'
                Info: 2: + IC(0.917 ns) + CELL(0.574 ns) = 2.526 ns; Loc. = LC_X5_Y5_N0; Fanout = 1; REG Node = 'i2c:u2|data_i_reg[7]'
                Info: Total cell delay = 1.609 ns ( 63.70 % )
                Info: Total interconnect delay = 0.917 ns ( 36.30 % )
            Info: - Longest clock path from clock "SCL" to source register is 2.526 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_64; Fanout = 36; CLK Node = 'SCL'
                Info: 2: + IC(0.917 ns) + CELL(0.574 ns) = 2.526 ns; Loc. = LC_X6_Y6_N5; Fanout = 15; REG Node = 'i2c:u2|index[8]'
                Info: Total cell delay = 1.609 ns ( 63.70 % )
                Info: Total interconnect delay = 0.917 ns ( 36.30 % )
        Info: - Micro clock to output delay of source is 0.235 ns
        Info: - Micro setup delay of destination is 0.208 ns
    Info: - Longest register to register delay is 3.896 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y6_N5; Fanout = 15; REG Node = 'i2c:u2|index[8]'
        Info: 2: + IC(0.592 ns) + CELL(0.571 ns) = 1.163 ns; Loc. = LC_X6_Y6_N1; Fanout = 6; COMB Node = 'i2c:u2|data_i_reg~2'
        Info: 3: + IC(1.602 ns) + CELL(0.319 ns) = 3.084 ns; Loc. = LC_X5_Y5_N2; Fanout = 1; COMB Node = 'i2c:u2|data_i_reg~3'
        Info: 4: + IC(0.443 ns) + CELL(0.369 ns) = 3.896 ns; Loc. = LC_X5_Y5_N0; Fanout = 1; REG Node = 'i2c:u2|data_i_reg[7]'
        Info: Total cell delay = 1.259 ns ( 32.32 % )
        Info: Total interconnect delay = 2.637 ns ( 67.68 % )
Warning: Can't achieve timing requirement Clock Setup: 'SCL' along 76 path(s). See Report window for details.
Info: No valid register-to-register data paths exist for clock "SDA"
Info: Slack time is 151 ps for clock "CLOCK_X" between source register "counter:u1|counter_x[1]" and destination register "counter:u1|counter_x[26]"
    Info: Fmax is restricted to 250.0 MHz due to tcl and tch limits
    Info: + Largest register to register requirement is 3.557 ns
        Info: + Setup relationship between source and destination is 4.000 ns
            Info: + Latch edge is 4.000 ns
                Info: Clock period of Destination clock "CLOCK_X" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "CLOCK_X" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLOCK_X" to destination register is 2.610 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_14; Fanout = 36; CLK Node = 'CLOCK_X'
                Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.610 ns; Loc. = LC_X5_Y7_N0; Fanout = 4; REG Node = 'counter:u1|counter_x[26]'
                Info: Total cell delay = 1.609 ns ( 61.65 % )
                Info: Total interconnect delay = 1.001 ns ( 38.35 % )
            Info: - Longest clock path from clock "CLOCK_X" to source register is 2.610 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_14; Fanout = 36; CLK Node = 'CLOCK_X'
                Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.610 ns; Loc. = LC_X2_Y7_N5; Fanout = 4; REG Node = 'counter:u1|counter_x[1]'
                Info: Total cell delay = 1.609 ns ( 61.65 % )
                Info: Total interconnect delay = 1.001 ns ( 38.35 % )
        Info: - Micro clock to output delay of source is 0.235 ns
        Info: - Micro setup delay of destination is 0.208 ns
    Info: - Longest register to register delay is 3.406 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y7_N5; Fanout = 4; REG Node = 'counter:u1|counter_x[1]'
        Info: 2: + IC(0.557 ns) + CELL(0.611 ns) = 1.168 ns; Loc. = LC_X2_Y7_N5; Fanout = 2; COMB Node = 'counter:u1|counter_x[1]~52'
        Info: 3: + IC(0.000 ns) + CELL(0.077 ns) = 1.245 ns; Loc. = LC_X2_Y7_N6; Fanout = 2; COMB Node = 'counter:u1|counter_x[2]~44'
        Info: 4: + IC(0.000 ns) + CELL(0.077 ns) = 1.322 ns; Loc. = LC_X2_Y7_N7; Fanout = 2; COMB Node = 'counter:u1|counter_x[3]~36'
        Info: 5: + IC(0.000 ns) + CELL(0.077 ns) = 1.399 ns; Loc. = LC_X2_Y7_N8; Fanout = 2; COMB Node = 'counter:u1|counter_x[4]~28'
        Info: 6: + IC(0.000 ns) + CELL(0.249 ns) = 1.648 ns; Loc. = LC_X2_Y7_N9; Fanout = 6; COMB Node = 'counter:u1|counter_x[5]~20'
        Info: 7: + IC(0.000 ns) + CELL(0.153 ns) = 1.801 ns; Loc. = LC_X3_Y7_N4; Fanout = 6; COMB Node = 'counter:u1|counter_x[10]~48'
        Info: 8: + IC(0.000 ns) + CELL(0.218 ns) = 2.019 ns; Loc. = LC_X3_Y7_N9; Fanout = 6; COMB Node = 'counter:u1|counter_x[15]~7'
        Info: 9: + IC(0.000 ns) + CELL(0.153 ns) = 2.172 ns; Loc. = LC_X4_Y7_N4; Fanout = 6; COMB Node = 'counter:u1|counter_x[20]~26'
        Info: 10: + IC(0.000 ns) + CELL(0.218 ns) = 2.390 ns; Loc. = LC_X4_Y7_N9; Fanout = 6; COMB Node = 'counter:u1|counter_x[25]~56'
        Info: 11: + IC(0.000 ns) + CELL(1.016 ns) = 3.406 ns; Loc. = LC_X5_Y7_N0; Fanout = 4; REG Node = 'counter:u1|counter_x[26]'
        Info: Total cell delay = 2.849 ns ( 83.65 % )
        Info: Total interconnect delay = 0.557 ns ( 16.35 % )
Info: Minimum slack time is 1.036 ns for clock "CLOCK_R" between source register "counter:u1|counter_ru[29]" and destination register "counter:u1|counter_ru[29]"
    Info: + Shortest register to register delay is 0.939 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y5_N9; Fanout = 4; REG Node = 'counter:u1|counter_ru[29]'
        Info: 2: + IC(0.570 ns) + CELL(0.369 ns) = 0.939 ns; Loc. = LC_X3_Y5_N9; Fanout = 4; REG Node = 'counter:u1|counter_ru[29]'
        Info: Total cell delay = 0.369 ns ( 39.30 % )
        Info: Total interconnect delay = 0.570 ns ( 60.70 % )
    Info: - Smallest register to register requirement is -0.097 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "CLOCK_R" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "CLOCK_R" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "CLOCK_R" to destination register is 2.610 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_12; Fanout = 72; CLK Node = 'CLOCK_R'
                Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.610 ns; Loc. = LC_X3_Y5_N9; Fanout = 4; REG Node = 'counter:u1|counter_ru[29]'
                Info: Total cell delay = 1.609 ns ( 61.65 % )
                Info: Total interconnect delay = 1.001 ns ( 38.35 % )
            Info: - Shortest clock path from clock "CLOCK_R" to source register is 2.610 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_12; Fanout = 72; CLK Node = 'CLOCK_R'
                Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.610 ns; Loc. = LC_X3_Y5_N9; Fanout = 4; REG Node = 'counter:u1|counter_ru[29]'
                Info: Total cell delay = 1.609 ns ( 61.65 % )
                Info: Total interconnect delay = 1.001 ns ( 38.35 % )
        Info: - Micro clock to output delay of source is 0.235 ns
        Info: + Micro hold delay of destination is 0.138 ns
Info: Minimum slack time is 1.025 ns for clock "SCL" between source register "i2c:u2|index[5]" and destination register "i2c:u2|index[6]"
    Info: + Shortest register to register delay is 0.928 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y5_N3; Fanout = 1; REG Node = 'i2c:u2|index[5]'
        Info: 2: + IC(0.559 ns) + CELL(0.369 ns) = 0.928 ns; Loc. = LC_X9_Y5_N1; Fanout = 1; REG Node = 'i2c:u2|index[6]'
        Info: Total cell delay = 0.369 ns ( 39.76 % )
        Info: Total interconnect delay = 0.559 ns ( 60.24 % )
    Info: - Smallest register to register requirement is -0.097 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "SCL" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "SCL" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "SCL" to destination register is 2.526 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_64; Fanout = 36; CLK Node = 'SCL'
                Info: 2: + IC(0.917 ns) + CELL(0.574 ns) = 2.526 ns; Loc. = LC_X9_Y5_N1; Fanout = 1; REG Node = 'i2c:u2|index[6]'
                Info: Total cell delay = 1.609 ns ( 63.70 % )
                Info: Total interconnect delay = 0.917 ns ( 36.30 % )
            Info: - Shortest clock path from clock "SCL" to source register is 2.526 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_64; Fanout = 36; CLK Node = 'SCL'
                Info: 2: + IC(0.917 ns) + CELL(0.574 ns) = 2.526 ns; Loc. = LC_X9_Y5_N3; Fanout = 1; REG Node = 'i2c:u2|index[5]'
                Info: Total cell delay = 1.609 ns ( 63.70 % )
                Info: Total interconnect delay = 0.917 ns ( 36.30 % )
        Info: - Micro clock to output delay of source is 0.235 ns
        Info: + Micro hold delay of destination is 0.138 ns
Info: Minimum slack time is 1.192 ns for clock "CLOCK_X" between source register "counter:u1|count_x" and destination register "counter:u1|count_x"
    Info: + Shortest register to register delay is 1.095 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y6_N7; Fanout = 4; REG Node = 'counter:u1|count_x'
        Info: 2: + IC(0.593 ns) + CELL(0.502 ns) = 1.095 ns; Loc. = LC_X4_Y6_N7; Fanout = 4; REG Node = 'counter:u1|count_x'
        Info: Total cell delay = 0.502 ns ( 45.84 % )
        Info: Total interconnect delay = 0.593 ns ( 54.16 % )
    Info: - Smallest register to register requirement is -0.097 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "CLOCK_X" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "CLOCK_X" is 4.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "CLOCK_X" to destination register is 2.610 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_14; Fanout = 36; CLK Node = 'CLOCK_X'
                Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.610 ns; Loc. = LC_X4_Y6_N7; Fanout = 4; REG Node = 'counter:u1|count_x'
                Info: Total cell delay = 1.609 ns ( 61.65 % )
                Info: Total interconnect delay = 1.001 ns ( 38.35 % )
            Info: - Shortest clock path from clock "CLOCK_X" to source register is 2.610 ns
                Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_14; Fanout = 36; CLK Node = 'CLOCK_X'
                Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.610 ns; Loc. = LC_X4_Y6_N7; Fanout = 4; REG Node = 'counter:u1|count_x'
                Info: Total cell delay = 1.609 ns ( 61.65 % )
                Info: Total interconnect delay = 1.001 ns ( 38.35 % )
        Info: - Micro clock to output delay of source is 0.235 ns
        Info: + Micro hold delay of destination is 0.138 ns
Info: tsu for register "i2c:u2|data[0]" (data pin = "SDA", clock pin = "SCL") is 2.025 ns
    Info: + Longest pin to register delay is 4.343 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_62; Fanout = 1; CLK Node = 'SDA'
        Info: 2: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = IOC_X13_Y4_N4; Fanout = 3; COMB Node = 'SDA~0'
        Info: 3: + IC(3.133 ns) + CELL(0.175 ns) = 4.343 ns; Loc. = LC_X8_Y5_N0; Fanout = 3; REG Node = 'i2c:u2|data[0]'
        Info: Total cell delay = 1.210 ns ( 27.86 % )
        Info: Total interconnect delay = 3.133 ns ( 72.14 % )
    Info: + Micro setup delay of destination is 0.208 ns
    Info: - Shortest clock path from clock "SCL" to destination register is 2.526 ns
        Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_64; Fanout = 36; CLK Node = 'SCL'
        Info: 2: + IC(0.917 ns) + CELL(0.574 ns) = 2.526 ns; Loc. = LC_X8_Y5_N0; Fanout = 3; REG Node = 'i2c:u2|data[0]'
        Info: Total cell delay = 1.609 ns ( 63.70 % )
        Info: Total interconnect delay = 0.917 ns ( 36.30 % )
Info: tco from clock "SCL" to destination pin "SDA" through register "i2c:u2|sda_io_reg~en" is 6.219 ns
    Info: + Longest clock path from clock "SCL" to source register is 2.526 ns
        Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_64; Fanout = 36; CLK Node = 'SCL'
        Info: 2: + IC(0.917 ns) + CELL(0.574 ns) = 2.526 ns; Loc. = LC_X7_Y6_N9; Fanout = 1; REG Node = 'i2c:u2|sda_io_reg~en'
        Info: Total cell delay = 1.609 ns ( 63.70 % )
        Info: Total interconnect delay = 0.917 ns ( 36.30 % )
    Info: + Micro clock to output delay of source is 0.235 ns
    Info: + Longest register to pin delay is 3.458 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y6_N9; Fanout = 1; REG Node = 'i2c:u2|sda_io_reg~en'
        Info: 2: + IC(2.004 ns) + CELL(1.454 ns) = 3.458 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'SDA'
        Info: Total cell delay = 1.454 ns ( 42.05 % )
        Info: Total interconnect delay = 2.004 ns ( 57.95 % )
Info: Longest tpd from source pin "CLOCK_X" to destination pin "LED[5]" is 4.006 ns
    Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_14; Fanout = 36; CLK Node = 'CLOCK_X'
    Info: 2: + IC(1.517 ns) + CELL(1.454 ns) = 4.006 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'LED[5]'
    Info: Total cell delay = 2.489 ns ( 62.13 % )
    Info: Total interconnect delay = 1.517 ns ( 37.87 % )
Info: th for register "i2c:u2|start_neg" (data pin = "SCL", clock pin = "SDA") is 0.147 ns
    Info: + Longest clock path from clock "SDA" to destination register is 3.197 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_62; Fanout = 1; CLK Node = 'SDA'
        Info: 2: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = IOC_X13_Y4_N4; Fanout = 3; COMB Node = 'SDA~0'
        Info: 3: + IC(1.588 ns) + CELL(0.574 ns) = 3.197 ns; Loc. = LC_X9_Y5_N4; Fanout = 20; REG Node = 'i2c:u2|start_neg'
        Info: Total cell delay = 1.609 ns ( 50.33 % )
        Info: Total interconnect delay = 1.588 ns ( 49.67 % )
    Info: + Micro hold delay of destination is 0.138 ns
    Info: - Shortest pin to register delay is 3.188 ns
        Info: 1: + IC(0.000 ns) + CELL(1.035 ns) = 1.035 ns; Loc. = PIN_64; Fanout = 36; CLK Node = 'SCL'
        Info: 2: + IC(1.376 ns) + CELL(0.777 ns) = 3.188 ns; Loc. = LC_X9_Y5_N4; Fanout = 20; REG Node = 'i2c:u2|start_neg'
        Info: Total cell delay = 1.812 ns ( 56.84 % )
        Info: Total interconnect delay = 1.376 ns ( 43.16 % )
Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 130 megabytes
    Info: Processing ended: Sun May 23 18:00:21 2010
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02